It is known that unprotected chip edges, in particular and in addition their corners, are extremely sensitive to mechanical loads, for example shocks. The resultant damage results in high failure rates during handling. In addition, any thermal/mechanical mismatch between the materials that are used for the electronic components can frequently lead to mechanical stress at the chip edges and at their corners, and in the process can lead to damage. Furthermore, unprotected fuses, which should be understood as meaning electrical fuses, e.g., for the provision of redundancy, are very sensitive to environmental influences, such as moisture and ions, and can thus corrode very easily.
In order to reduce or to avoid these problems, various more or less complex methods and arrangements for protection of the semiconductor chips have become known. For example, it is possible to dispense an underfiller around the chip edges, in order to protect them. See U.S. Pat. No. 5,920,118. A suitable interposer can also be used, or else a suitable plastic can be printed, or else the electronic component can be encapsulated (molded) in order to achieve complete protection for the semiconductor chip.
U.S. Pat. No. 6,225,144 describes a method and a device for underfilling the intermediate space between a chip and a substrate with an underfilling material. U.S. Pat. No. 5,659,952 describes the production of a compliant interface for a semiconductor chip which is electrically connected to a substrate by means of solder balls. Here, the intermediate space between the chip and the substrate is filled with a compliant filling compound.
However, it has been found that the effects of the thermomechanical stresses, which occur during operation of the electronic components cannot be effectively counteracted by the described methods.
Attempts have also been made to reduce thermomechanical stresses by suitable selection of the components, as has been described for a chip-scale (CSP) component in US Patent Application No. 2001/0046120.
Another possible way to reduce thermomechanical stress is described, for example, in U.S. Pat. No. 5,293,067, which describes a chip mount for integrated circuits, in which a semiconductor chip is connected electrically and at the same time mechanically to a substrate via bumps (solder balls) and contact islands (pads). In order to achieve a better mechanical connection between the semiconductor chip and the substrate as well, the intermediate space between the components is filled with an organic connecting means (underfiller), such as an epoxy resin or silicone. This underfiller is also intended to be used to reduce mechanical loads (stress) between the semiconductor chip and the substrate. Furthermore, the underfiller also has the function of protecting the active areas and the electrical connections against environmental influences. Depending on the application, the underfiller may in this case fill the entire intermediate space between the components, or possibly only the area of the active surface of the semiconductor chip. However, effective edge protection for the semiconductor chip is not possible with this arrangement.
A completely different embodiment of a sheath for a semiconductor chip is described in U.S. Pat. No. 6,124,546. In this case, a semiconductor chip is mounted on the interconnects of an upper interposer by means of solder balls. Two or more spacers composed of an insulator material, for example an elastomer, are arranged on the rear face of the chip, and a second interposer is mounted on them, which is at the same time provided with external contacts (BGA) for making contact between the module and printed circuit boards, etc. The intermediate space between the two interposers is filled with an encapsulating compound. Since the semiconductor chip is in this case surrounded on all sides, this encapsulation admittedly provides good protection for the semiconductor chip, but even this does not ensure adequate protection against thermomechanical loads. A further disadvantage is that it is impossible to achieve particularly small dimensions, for example in the case of CSP (Chip Scale Packages), that is to say the range of applications is restricted.